The present invention relates generally to metal oxide semiconductor field effect transistors (MOSFETS) and more particularly to vertical, grooved MOSFET (VMOS) devices, and vertical, double diffused MOSFET (VDMOS) devices.
A typical MOSFET structure comprises a semiconductor substrate which includes adjacent source, body and drain regions of alternate (i.e., P or N) conductivity type. In a vertical MOSFET the source and drain regions are on opposite semiconductor major surfaces and yield a vertical current flow (perpendicular to the surfaces) through the device. In a VDMOS device the semiconductor substrate is substantially planar in configuration. The body region is adjacent to one of the planar surfaces and the gate, comprising an electrode disposed over an oxide, is disposed on the surface over the body region. In a VMOS structure a groove in one of the semiconductor surfaces intersects the body region, and the gate is disposed within the groove over the body region.
When a VDMOS or VMOS device is appropriately biased, majority charge carriers flow from the source, through a channel (in a surface portion of the body region under the gate), to the drain. The device is thus unipolar in nature. However, the existence of PN junctions between the source and body and between the body and drain create the possibility for minority charge carrier flow (i.e., a parasitic bipolar transistor) as well. Since the efficiency of the unipolar MOSFET is degraded by this bipolar transistor it is desirable to minimize the minority carrier flow. The present invention provides a vertical MOSFET structure having minimized parasitic bipolar effects and a method for fabricating a VMOS structure.